The present disclosure is related to semiconductor devices and, more particularly, to thyristor semiconductor memory devices and their methods of manufacture.
Advancement of the semiconductor industry has brought about devices of decreased size and greater density for enabling higher levels of integration. Enabling some of these advancements, the silicon-on-insulator (SOI) technology provides for a layer of silicon over an insulator such as oxide. If the layer of silicon is made sufficiently thin, a voltage biased electrode thereover may be capable of fully depleting carriers within the silicon layer. Such structured devices may be described as fully depleting SOI devices and may be seen to enable further reductions in device geometries while at the same time enabling greater control of certain leakage characteristics.
In the case of a metal-oxide-semiconductor field-effect transistor (MOSFET), a gate electrode may be disposed in insulated, spaced relationship over a channel region within a layer of silicon. When biased, the gate electrode may produce an electric field in the channel to control conductivity thereof between the source and drain regions of the MOSFET. For example, in an N type MOSFET, when charged positively, the gate electrode may attract negative carriers from within the channel toward a surface region thereof proximate and beneath the gate electrode. Assuming, in this example, that the channel may comprise P-type silicon disposed between N-doped source and drain regions, the positively charged gate electrode, thus, may be described as attracting “minority” carriers (electrons) from within the P-type channel toward the surface region just beneath the insulated gate electrode. Once a sufficient number of these carriers have been accumulated at the surface region beneath the insulated gate electrode, an “N-Channel” is formed therein and may be capable of passing charge between the source and drain regions. For such device, reducing the thickness of the channel region may allow tighter coupling and responsiveness therefore to be established between the bias level of the gate electrode and the conductivity of the channel between the source and drain regions. Additionally, a shorter length for the channel between the source and drain regions may allow charge to flow through the channel in less time, which in turn may permit faster operating speeds for the MOSFET.
Previously, the dimensions of these MOSFET devices have been limited by the minimum line widths by which gate electrodes could be formed over the channel regions. In the past, these minimum line widths had typically been limited by the resolution associated with photolithographic processes. More recently, however, MOSFET devices have been fabricated with use of replacement gate processes. Such replacement gate processes have enabled the formation of channels with lengths less than, e.g., 100 nm. The gate structures that may result from these replacement gate processes may be characterized as T-gates. As will be more fully disclosed herein, the T-gate may comprise a leg or foot portion thereof slotted between dielectric sidewalls. The dielectric sidewalls may comprise part of a trench that has been previously formed in the dielectric over the silicon layer. The foot may have a narrow width that is positioned over the channel region. Arms of the T-gate, however, may extend outwardly over the top to establish a broad width. This broad upper width may increase an overall cross-sectional area for the gate electrode to reduce its resistivity. Additionally, the top surface and sidewalls of the arms (or shoulders) associated with the T-gate may be treated with silicide to assist further reduction in resistivity of the gate electrode along its length.
In the case of fabricating a thin capacitively coupled thyristor (TCCT) device, a capacitor electrode may be formed over and capacitively coupled to a base region of the thyristor. The capacitor electrode may be driven as a wordline over the base region for capacitively coupling to the base to manipulate the voltage of the base region during certain electrical operations of the thyristor. For example, when trying to shutdown a current flow through the thyristor, it may be helpful to activate the capacitor electrode with a potential that may speed up the removal of minority carriers from within the base region. By such capacitor electrode or wordline activation, the operating state of the thyristor may transition more rapidly than what might otherwise be available by merely waiting for the decay/persistence/lifetime property of the minority carriers within the base region.
When fabricating TCCT devices, it may be necessary to form a second base region for the thyristor at a position that is offset from the capacitor electrode that is coupled to the first base region. The offset may allow activation of the capacitor electrode with reduced leakage (e.g., GIDL type) effects from the capacitor electrode upon the second base region. Typically, the fabrication techniques for the capacitor electrode for these TCCT devices have employed photolithographic procedures for forming (i) a rectangular cross-section for the capacitor electrode with a width thereof over the first base region, and (ii) forming the second base region offset from the gate electrode. Additionally, the silicide formations over the thyristor's emitter regions typically may use separate photolithographic and masking provisions for keeping the silicide separate and isolated from the first and second based regions. These type of fabrication procedures for the thin capacitively coupled thyristor (TCCT) devices could be viewed as consuming, utilizing and/or requiring large amounts of semiconductor real-estate across, e.g., an SOI substrate, which in turn would affect costs.
It may be noted, therefore, that the typical procedures for the formation of thin capacitively coupled thyristor devices, which have been formed differently relative to the procedures for SLOTFETs, might thus add to complexity, cost and size when integrated therewith in forming semiconductor devices such as thyristor memory and other embedded semiconductor systems.